MCQ Bank

Amdahl's law describes the limit on speedup from parallelization based on the:

Multicore processors improve performance primarily by:

The system bus of a computer typically consists of the data bus, control bus, and:

The clock speed of a CPU is measured in:

A CISC architecture is characterized by:

Harvard architecture differs from von Neumann architecture by using:

Von Neumann architecture is characterized by:

A pipeline hazard that arises when an instruction depends on the result of a previous instruction still in the pipeline is a:

A word in computer architecture refers to:

A RISC (Reduced Instruction Set Computer) architecture is characterized by:

The principle of locality of reference explains why which component is effective?

The control unit of a CPU is responsible for:

Which of the following is a non-volatile type of memory?

The arithmetic logic unit (ALU) of a CPU is responsible for:

Registers in a CPU are used to:

A cache hit occurs when:

An instruction set architecture (ISA) defines:

Pipelining in a processor improves performance by:

In the fetch-decode-execute cycle, the program counter (PC) holds:

Which type of memory is volatile, losing its contents when power is removed?